Maintaining High Throughput during Overload in ATM Switches

This paper analyzes two popular heuristics for ensur ing packet integrity in ATM switching systems In particular we analyze the behavior of packet tail dis carding in order to understand how the packet level link e ciency is dependent on the rates of individual virtual circuits and the degree of the imposed over load In addition we study early packet discard and show that the queue capacity needed to achieve high e ciency under worst case conditions grows with the number of virtual circuits and we determine the e ciency obtainable with more limited queue capacities Using the insights from these analyses extensions to early packet discard are proposed which achieve high e ciency with dramatically smaller queue capacities independent of the number of virtual circuits